1. Field of the Invention
This invention relates generally to a decoder and, more particularly, to a decoder for decoding address signals and a clock signal in a synchronous complementary metal-oxide-semiconductor memory (hereinafter referred to as a CMOS memory).
2. Description of the Prior Art
In recent years, large scale integrated circuits (hereinafter referred to as LSI) such as a random access memory (hereinafter referred to as RAM) or a read only memory (hereinafter referred to as ROM) have been manufactured by using CMOS technology. CMOS technology has a number of well known advantages, including low power consumption, wide voltage operating range, wide temperature operating range, and good noise immunity. The selection of a memory cell within the memory can be carried out by decoding address signals, on address lines which designate the location of the cell. Thus, after a desired cell is selected, the data stored in the cell is read out or new data is written into the cell.
While a row-address signal, in the row address lines is decoded by a group of row decoders, whose number is the same as that of the rows, a column-address signal in the column address lines is decoded by a group of column decoders, whose number is the same as that of the columns. These decoders associated with the memory cells are manufactured on a chip. Therefore, it is necessary to reduce the area of each of the decoders on the chip in order to obtain high integration of the memory chip.
A decoder used in a prior art asynchronous CMOS memory includes an MOS transistor of one conductivity-type, such as a p-channel MOS transistor to whose gate is applied an address signal and a plurality of MOS transistors of the opposite condutivity-type, such as n-channel MOS transistors, connected in series and having gates to which predetermined address signals are applied. The connecting point of the p-channel MOS transistor and the series-connected n-channel MOS transistors serves as an intermediate output terminal of the decoder (Ref.: IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-12, No. 5, Oct., 1977, pp. 502-506). For example, when the p-channel MOS transistor is non-conductive and all the n-channel MOS transistors are conductive, the decoder can select its corresponding row or column. However, in a memory decoded by using a plurality of the above-mentioned decoders, one memory cell is selected no matter what the address signal in the address lines may be. As a result, even during an operation in which no reading is involved, load transistors which are arranged in the bit lines at the selected memory cell are conductive, so that the data stored in the cell may be read out. The power consumption during such an operation is large. Therefore, it is necessary to eiminate the above-mentioned power consumption.
A prior art row decoder or column decoder used for a synchronous CMOS memory receives row-address signals or column-address signals, as well as a clock signal for disabling the entire chip of the memory, thereby eliminating the power consumption due to the useless reading-out operation. For example, the row decoder includes an MOS transistor of one conductivity-type, such as a p-channel MOS transistor, to whose gate is applied the clock signal, and a plurality of MOS transistors of the opposite conductivity-type, such as n-channel MOS transistors, connected in series. The clock signal is applied to the gate of one of the n-channel MOS transistors and each of the row-address signals is applied to the gates of the other n-channel MOS transistors, respectively. The connecting point of the p-channel MOS transistor and the series-connected n-channel MOS transistors serves as an intermediate output terminal of the decoder. For example, when the p-channel MOS transistor is non-conductive and all the n-channel MOS transistors are conductive, which means that the potential of the clock signal is high, the decoder can select its corresponding row. There are many row and column decoders in a chip. For example, there are 32, 64 and 128 row decoders in the 1K(32.times.32), 4K(64.times.64) and 16K(128.times.128) bit memory chips, respectively. Therefore, it is necessary to reduce the number of elements included in the decoders such as row decoders, in order to obtain high-density integration of the memory chip.